About the Role
Bachelor's degree or Master’s degree in Electronics or similar
Excellent problem-solving and troubleshooting skills.
Strong written, verbal, and telephonic communication skills.
Excellent research and interpersonal skills.
Strong analytical skills.
Requirements
Fundamentals of SCAN stuck-at and at-speed techniques
Expertise in handling Mentor Graphics EDT logic
Knowledge on On chip clock controller (OCC)
Pattern generation with Mentor Graphics TestKompress Tool
Good knowledge in BSCAN operations. Knowledge in MBIST Operations
Expertise in handling Synopsys SMS tool sets (Integrator, Builder, Yield Accelerator)
Excellent track of pattern simulation and coverage analysis (preferred cadence ncsim simulator expert Experience in ATPG, Scan, BIST and Mentor TestKompress
Expert in writing test benches (Verilog, system Verilog) and tests for different components like PLL, ADC etc for generating ATE vectors
Familiarity with scan, JTAG concepts and 3rd party tools
Tester program creation, debug, and validation of DFT features on ATE