ASIC Design
From RTL Netlist to GDSII: Engineering Tomorrow's Technology, Today!
About
Highlights
Experience with FinFET, CMOS, BCD and SOI
Technology experience on varying process nodes optimized for performance, power ranging from 28nm, 16nm, 10nm and 7nm
Collaboration with top-tier semiconductor fab houses
Multiple full chips and IP level tape out have been done successfully with first-pass silicon
Expertise
We spearhead the chip development process, laying the groundwork for the flawless execution of intricate semiconductor devices
- The placement and interconnection of functional blocks are precisely defined to ensure optimal performance within the available space
- Chip architectures are crafted by our team to balance desired functionality with minimal power consumption and footprint
- Strategic planning is applied to the chip architecture, prioritizing efficient power utilization, achieving desired performance targets and minimizing the overall chip area
Caliber provides RTL design services for IP and SOC development, starting from product specifications.
- Expertise in IP block Design and Development
- Proficiency across multiple sectors including automotive, networking, mobile, IoT, microprocessors, multimedia and cloud computing
- Track record in designing protocols like I2C, SPI, AMBA-AXI, AMBA-AHB, UVM, WISHBONE and UART model
- Extensively worked on IPs like high-speed interfaces, memory controllers, video codecs, networking, USB and PCIe
- Leading front-end tools (Synopsys, Cadence, Mentor) are leveraged for Lint, CDC, Low Power and Synthesis
We offer end-to-end design verification services, encompassing the full architecture, development of new test benches, transaction-level models, scoreboards and thorough coverage analysis.
- Exposure in verification methodologies like OVM, UVM and VMM
- SoC Verification
- Coverage and Formal Verification
- Power-aware verification
- VIP development
- VIP Integration
- Gate Level simulations
- Environment Architecture Development
RTL synthesis – (Logical and Physical Aware Synthesis) acts as the critical bridge between the high-level design concept and its physical realization in silicon.
- Transformation of RTL description to gate-level representation
- Management of area, power and timing
- Bridging high-level design with silicon implementation in the ASIC design flow
- Optimization techniques for technology mapping and logic restructuring
To develop and execute a comprehensive DFT strategy, enhancing IC testability in the post-silicon phase for seamless first-pass silicon.
- DFT architecture and scan methodology
- DFT (JTAG, SCAN, MBIST) insertion and verification
- ATPG pattern generation and Timing simulation
- Test coverage analysis and improvement
- DFT DRC checks and fixes
- Extensive support on DFT insertion and Simulations
- Deep support in industry standard tool sets
Our physical design team excels in the RTL-to-GDSII flow, emphasizing PPA optimization for advanced technology nodes and processes.
- Our extensive portfolio spans projects across diverse sectors, including Networking, Mobility, Automotive, Processor and Telecom designs. Through meticulous optimization of critical paths, innovative timing closure techniques and architectural advancements, we produce designs distinguished by their speed, throughput and responsiveness
- Our capabilities encompass the latest silicon processes, from 180nm down to 28nm, 14nm and leading-edge 7nm nodes
- Delivered turnkey solutions for SoCs and ASICs digital design, overseeing the entire process from specifications to silicon bring-up
- Achieving timing closure for high-frequency designs utilizing cutting-edge technology down to 7nm
- Creating timing specifications and comprehensive check lists for development purposes
- Comprehensive low-power design and test methodologies
