High complex ASIC/SOC devices that contains millions of logic and functional blocks operating at high frequency need a proper test strategy to achieve optimized fault coverage. Our DFT consultants provide solutions for the increasing complexity of test challenges in IC designs.

• DFT & DFD Architecture/Planning
• Top leadership has experience of more than 22 years which includes working in several well-known North American product companies (like AMD/Genesis/Teranitics/PLX) in DFT/DFD Principal architect position
• Handled more than 50 designs from architecture to silicon bring - up including high-speed processors/mixed-signal SOC products
• TAP controller (BSCAN) insertion
• Analog DFT
• DFD like test bus plan/scan dump etc
• RO/LBIST definition and spec
• DFT mode STA
• Multiple clock domain/power domain handling
• Pattern debug/yield enhancement
• RMA analysis

• —DFT/DFD architecture
• —SCAN insertion & ATPG pattern generation
• —MBIST with repair

We have 500 plus experienced design resources and offering our design and post silicon test services to top semiconductor companies. We maintain the best in class EDA  design infrastructure and processes specific to foundry to achieve optimum performance results.

Caliber Interconnect offers complete layout services from chip to package to PCB for the past 12 years.

Team expertise:

• RTL synthesis and DFT(scan , ATPG, MBIST, LBIST)
• Floor planning, place and route, IR drop analysis, power optimization
• Experience in deep sub micron node process
• High power and high frequency physical design capabilities

With a flexible working models, our experienced engineers undertake complete ownership of your physical design requirements.