The interconnects operating at high frequency, and fast switching rates demand SI analysis for the right design at the first time. Caliber Interconnect's SI engineers having strong knowledge of SI theory and expertise in simulation tools to analyze various SI/PI issues like reflection due to impedance mismatch, crosstalk, signal attenuation and PDN noise which affects the interconnect performance. The analysis is carried out in two phases, the pre and post- layout analysis.
Planning the stack-up for controlled impedance, dielectric material selection for high frequency operation, I/O buffer selection from different drive strengths, topology optimization, termination strategy, routing specifications(Trace width, spacing and length matching) and floor planning for critical components are various sections in pre-layout analysis.
Post layout analysis includes simulations of the routed board for potential SI/PI issues like reflection, overshoot/undershoot, crosstalk, attenuation, EMI and PDN issues. The post layout report is prepared from simulation results along with suggestions for topology modification, termination schemes and layout modification to achieve good signal and power integrity for any SI/PI issues
Caliber SI engineers are familiar with high speed channel modelling considering backplane, Add-in Card, via breakout, connectors and cables. Using highly accurate Ansys and Sigrity 3D simulation tools, we can do correct and optimized channel so as to keep the channel loss within the spec. Also, long SERDES channel with a high data rate needs the use of different TX pre-emphasis, RX CTLE gain and DFE equalization tap factors so that the eye opening is good at the Receiver end. These features are available in the ibis ami models. We have good experience in ami parameter variation and optimization for SERDES channel to keep the channel within the eye spec with the help of market leading simulation tools of the latest versions.
Signal Integrity Analysis
We have experience in carrying simulations involving the following interfaces: