Service Overview

Our experienced team will work hand in hand with you for rapid test bring up thereby reducing time to market and cost. We offer full test software / hardware development services for ATE and / or instrument based test routines & programs across all major IC types, covering characterization, NPI, probe & final test, across product life cycle and continuous improvement efforts, all types of test hardware including high speed / high density load boards, test hardware, necessary personalization kits for probers and handlers.

Our engineering team can also support characterization, 1st articles, 1st release probe/test solutions, leading to prototype/low volume production, then total alignment to transfer to HVM at the foundry, IDM or OSAT test floor(s). 

Value Proposition

Providing back-end IC test development to worldwide customers for over 20 years

Talent Engineering talent pool well beyond 70+, highly skilled in IC test development, ATE board design

Design & DFT backgrounds

Test Hardware experience

Work with designers at the pre silicon phase to enhance the test ability of silicon, greatly increasing the test coverage and effectiveness

Swift feasibility studies and test process timeline estimations projections

Deep and diverse product exposure and nimble adaption to any new test platform

TTR (Test time reduction) audits

Extended arm to customer's in house testing team, leveraging the time gap and expediting test development time either through remote or using in house testers

Process mechanisms to ensure utmost quality

Consistent upgrading of skills anticipating future needs of clients

Secure data network key for off-site development

Long term relationships with ATE tester suppliers, test hardware vendors, OSATs foundries and IDMs

Service Overview

In ATE testing, test development time plays a crucial part influencing time to market. With the increasing complexity and technology of SOC chips, the development time becomes even more critical. This paper deals with the possible automation of test development and describes about its implementation to effectively cut down test development time and manual efforts.

TestGeni, an intelligent automation tool developed by CIS generates a ready to load test flow from primary setup files. It reduces more than 60% of manual effort involved in test preparation. This tool accepts different formats of primary setup files from test engineers and creates a standard format file for supporting all ATE test platforms (e.g., V93000 SM7 and SM8; IG XL uFlex). It auto validates input parameters given by test engineers and generates pin configuration files (including mapping channels, grouping pins and ports, etc.) on its own and engenders loadable files of levels and time for DuT from the setup primary itself. Cross portability between production testing, characterization testing and debug test flow has also been supported in this tool. By generating vectors with any memory size with zero manual error, this tool goes a long way in reducing the manual effort in testing memory ICs.

It uses data analytic, data visualization techniques and fault detecting algorithms for automation. Also, this tool engenders test coverage reports and allows in test flow editing with a lot of ease.