Expertise in:
Design tools – mentor and allegro package designer
Cadence sigrity tools
The thermal and mechanical aspects of package design
Flip-chip, BGA, wire-bond BGA, chip-scale-package (CSP),Package on Package (PoP),
Package-in-Package (PiP) design, MLO/MLC package for ATE hardware
System-in-Package (SiP) design for applications such as cellular, bluetooth, WLAN, GPS, camera, PDA and CMOS sensor
Signal Integrity & Power Integrity analysis & optimization during early stage of package design
IC/Package/Board co - design flow
SSN analysis based on SI/PI, co - design flow using the SPICE netlist
Package RLC extraction & package model generation for SI/PI analysis
Power integrity and decoupling cap optimization
Thermal & mechanical design
Leading Provider of High Speed Design and Analysis Services for:
System in Packages (SiP) designs
Flipchip and Wirebond designs
Multi Chip Modules(MCMs) designs
MLO/MLC/Coreless/Hybrid Substrate
designs, Interposers for probe cards designs
Chip Scale Package designs
LTCC & HTCC designs
Chiplet designs
Specializing in design services for the medical and defence sectors
Highly Skilled Design/Analysis and Layout Team
More than 800+ package designs successfully completed
Organic build up from 1-2-1 to 15-24-15 layers
Low cost 4 layer laminates
Multi layer ceramic designs
Cost-Effective and Timely Job Completion
Lead Time 1 to 3 weeks from frozen netlist based on complexity
Advanced Tools
SIP4150SPB - Allegro (R) package designer plus
SIP226SPB - APD SiP layout option