Chip Solutions

IC Package Design

Just Bond The Dies

IC Package Design

IC package design services flip-chip, wire-bond, stacked-die, System-in-Package (SiP), Package-on-Package (PoP), Package-in-Package (PiP), Chip-Scale-Package (CSP) 

Vertical space transformers (MLO/MLC) for ATE testing applications. high - speed digital ICs, mixed-signal ICs and RFIC products

High degree of expertise and careful signal integrity & power integrity analysis

Strong capability to perform simultaneous - switching - noise (SSN) SI/PI simulations, parasitic package extractions

System - level SI timing analysis and Power integrity optimization using the latest Ansys

Cadence sigrity tools

Thermal and mechanical aspect of package design

Flip-Chip, BGA, Wire-bond BGA, Chip-Scale-Package (CSP), Package-on-Package (PoP), Package-in-Package (PiP) design, MLO/MLC package for ATE hardware

System-in-Package (SiP) design for applications such as cellular, bluetooth, WLAN, GPS, camera, PDA and CMOS sensor

Signal Integrity & Power Integrity analysis & optimization during early stage of package design

IC/Package/Board co - design flow

SSN analysis based on SI/PI, co - design flow using the SPICE netlist

Package RLC extraction & package model generation for SI/PI analysis

Power Integrity and decoupling cap optimization

Design tools – Mentor and Allegro package designer

Thermal & mechanical design

Coordination with assembly-house and substrate foundry to achieve the first- time right substrate

Strict adherence to assembly specifications

Experienced CAM team validates the design for fab house DFM specification

Leading Provider Of High Speed Design And Analysis Services For:

Probe cards

System in packages (SiP)

Multi-layer package designing and layouts

Multi chip modules (MCMs)

MLO/MLC substrate designs

Highly Skilled Design/Analysis And Layout Team

More than 800+ package designs successfully completed

Organic build up from 1-2-1 to 10-16-10 layers

Low cost 4 layers laminates

Multi layer ceramic designs

Cost-Effective And Timely Job Completion

Lead Time 1.5 to 3 weeks from frozen netlist based on complexity

Advanced Tools

SIP4150SPB - Allegro (R) package designer plus

SIP226SPB - APD SiP layout option