Chip Solutions


Cost-Effective Service Optimized For Your Design

Design Verification Silicon Frontend – DV

Our ASIC/FPGA verification experts will assist you in creating a test plans and test benches to assist


Design verification (DV) at RTL level and at gate level (i.e. gate level simulations – both unit delay and SDF annotated)

Power-aware verification

Formal verification

Experience in verification infrastructure development (including stimulus generator, driver, monitor, scoreboard, assertions, CP coding)

Experience in languages like verilog, system verilog, specman, vera, C++, C and system C

Experience with tools like modelsim, NCSim, VCS, debussy, MVSIM, MVRC, JasperGold

Senior management have experience of more than 12 years in DV area

Design For Test And Debug DFT/DFD

Today's highly complex ASIC/SOC devices, containing millions of logic and functional blocks need a proper test strategy to achieve optimized fault coverage. Our DFT consultants provide solutions for the increasing complexity of test challenges in IC designs.


DFT & DFD Architecture/Planning

Engineers with an average 15 years experience

Clients past & present: AMD/Genesis/Teranitics/PLX)

Handled more than 50 designs from architecture to silicon bring - up including high-speed processors/mixed-signal SOC products

TAP controller (BSCAN) insertion

Analog DFT

DFD like test bus plan/scan dump etc

RO/LBIST definition and spec

DFT mode STA

Multiple clock & power domains

Pattern debug/yield enhancement

RMA analysis

SCAN insertion & ATPG pattern generation

MBIST with repair

Physical Design

We have 500 plus experienced design resources and offering our design and post silicon test services to top semiconductor companies. We maintain the best in class EDA design infrastructure and processes specific to foundry to achieve optimum performance results.

CIS offers complete layout services from chip to package to PCB for the past 12 years.


RTL synthesis and DFT(scan , ATPG, MBIST, LBIST)
Floor planning, place and route, IR drop analysis, power optimization
High power and high frequency physical design capabilities With a flexible working models, our experienced engineers undertake complete ownership of your physical design requirements
Experience in deep sub micron node process